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8 8 1 8 1 1 1 2 3 4 5 6 7 8 n/c _ v cc v e v o gnd + n/c v f features ? very high speed-10 mbit/s superior cmr-10 kv/s double working voltage-480v fan-out of 8 over -40c to +85c logic gate output strobable output wired or-open collector u.l. recognized (file # e90700) description the 6n137, hcpl-2601/2611 single-channel and hcpl-2630/2631 dual-channel optocouplers consist of a 850 nm algaas led, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. this output features an open collector, thereby permitting wired or outputs. the coupled parameters are guaranteed over the temperature range of -40c to +85c. a maximum input signal of 5 ma will provide a minimum output sink current of 13 ma (fan out of 8). an internal noise shield provides superior common mode rejection of typically 10 kv/s. the hcpl- 2601 and hcpl- 2631 has a minimum cmr of 5 kv/s. the hcpl-2611 has a minimum cmr of 10 kv/s. applications ground loop elimination lsttl to ttl, lsttl or 5-volt cmos line receiver, data transmission data multiplexing switching power supplies pulse transformer replacement computer-peripheral interface input enable output hhl lhh hlh llh hncl lnch a 0.1 f bypass capacitor must be connected between pins 8 and 5. (see note 1) truth table (positive logic) 1 2 3 4 5 6 7 8 + _ v f1 v cc v 01 v 02 gnd v f2 _ + hcpl-2630 hcpl-2631 6n137 hcpl-2601 hcpl-2611 high speed-10 mbit/s logic gate optocouplers ? ? 2001 fairchild semiconductor corporation ds300202 7/9/01 1 of 11 www.fairchildsemi.com single-channel dual-channel 6n137 hcpl-2630 hcpl-2601 hcpl-2631 hcpl-2611
recommended operating conditions parameter symbol min max units input current, low level i fl 0 250 a input current, high level i fh *6.3 15 ma supply voltage, output v cc 4.5 5.5 v enable voltage, low level v el 0 0.8 v enable voltage, high level v eh 2.0 v cc v low level supply current t a -40 +85 c fan out (ttl load) n 8 parameter symbol value units storage temperature t stg -55 to +125 c operating temperature t opr -40 to +85 c lead solder temperature t sol 260 for 10 sec c emitter dc/average forward single channel i f 50 ma input current dual channel (each channel) 30 enable input voltage single channel v e 5.5 v not to exceed v cc by more than 500 mv reverse input voltage each channel v r 5.0 v power dissipation single channel p i 100 mw dual channel (each channel) 45 detector supply voltage v cc 7.0 v (1 minute max) output current single channel i o 50 ma dual channel (each channel) 50 output voltage each channel v o 7.0 v collector output single channel p o 85 mw power dissipation dual channel (each channel) 60 absolute maximum ratings (no derating required up to 85 c) * 6.3 ma is a guard banded value which allows for at least 20 % ctr degradation. initial input current threshold value is 5.0 m a or less high speed-10 mbit/s logic gate optocouplers www.fairchildsemi.com 2 of 11 7/9/01 ds300202 single-channel dual-channel 6n137 hcpl-2630 hcpl-2601 hcpl-2631 hcpl-2611
ac characteristics test conditions symbol min typ** max unit propagation delay time (note 4) (t a =25 c) t plh 20 45 75 ns to output high level (r l = 350 1 , c l = 15 pf) (fig. 12) 100 propagation delay time (note 5) (t a =25 c) t phl 25 45 75 ns to output low level (r l = 350 1 , c l = 15 pf) (fig. 12) 100 pulse width distortion (r l = 350 1 , c l = 15 pf) (fig. 12) t phl -t plh 335ns output rise time (10-90%) (r l = 350 1 , c l = 15 pf) t r 50 ns (note 6) (fig. 12) output fall time (90-10%) (r l = 350 1 , c l = 15 pf) t f 12 ns (note 7) (fig. 12) enable propagation delay time (i f = 7.5 ma, v eh = 3.5 v) t elh 20 ns to output high level (r l = 350 1 , c l = 15 pf) (note 8) (fig. 13) enable propagation delay time (i f = 7.5 ma, v eh = 3.5 v) t ehl 20 ns to output low level (r l = 350 1 , c l = 15 pf) (note 9) (fig. 13) common mode transient immunity (t a =25 c) v cm = 50 v, (peak) (at output high level) (i f = 0 ma, v oh (min.) = 2.0 v) cm h v/? 6n137, hcpl-2630 (r l = 350 1 ) (note 10) 10,000 hcpl-2601, hcpl-2631 (fig. 14) 5000 10,000 hcpl-2611 v cm = 400 v 10,000 15,000 (r l = 350 1 ) (i f = 7.5 ma, v ol (max.) = 0.8 v) 10,000 common mode 6n137, hcpl-2630 v cm = 50 v (peak) cm l v/? transient immunity hcpl-2601, hcpl-2631 (t a =25 c) 5000 10,000 (at output low level) (note 11) (fig. 14) hcpl-2611 (t a =25 c) v cm = 400 v 10,000 15,000 switching characteristics (t a = -40 c to +85 c, v cc = 5 v, i f = 7.5 ma unless otherwise specified.) parameter test conditions symbol min typ** max unit emitter (i f = 10 ma) v f 1.8 v input forward voltage t a =25 c 1.4 1.75 input reverse breakdown voltage (i r = 10 ?) b vr 5.0 v input capacitance (v f = 0, f = 1 mhz) c in 60 pf input diode temperature coefficient (i f = 10 ma) v f / t a -1.4 mv/ c detector 710 high level supply current single channel (v cc = 5.5 v, i f = 0 ma) i cch ma dual channel (v e = 0.5 v) 10 15 low level supply current single channel (v cc = 5.5 v, i f = 10 ma) i ccl 913 ma dual channel (v e = 0.5 v) 14 21 low level enable current (v cc = 5.5 v, v e = 0.5 v) i el -0.8 -1.6 ma high level enable current (v cc = 5.5 v, v e = 2.0 v) i eh -0.6 -1.6 ma high level enable voltage (v cc = 5.5 v, i f = 10 ma) v eh 2.0 v low level enable voltage (v cc = 5.5 v, i f = 10 ma) (note 3) v el 0.8 v individual component characteristics electrical characteristics (t a = -40 c to +85 c unless otherwise specified.) high speed-10 mbit/s logic gate optocouplers ds300202 7/9/01 3 of 11 www.fairchildsemi.com single-channel dual-channel 6n137 hcpl-2630 hcpl-2601 hcpl-2631 hcpl-2611
characteristics test conditions symbol min typ** max unit input-output (relative humidity = 45%) insulation leakage current (t a = 25 c, t = 5 s) i i-o 1.0* a (v i-o = 3000 vdc) (note 12) withstand insulation test voltage (rh < 50%, t a = 25 c) v iso 2500 v rms (note 12) ( t = 1 min.) resistance (input to output) (v i-o = 500 v) (note 12) r i-o 10 12 1 capacitance (input to output) (f = 1 mhz) (note 12) c i-o 0.6 pf isolation characteristics (t a = -40 c to +85 c unless otherwise specified.) ** all typical values are at v cc = 5 v, t a = 25 c 1. the v cc supply to each optoisolator must be bypassed by a 0.1? capacitor or larger. this can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package v cc and gnd pins of each device. 2. each channel. 3. enable input - no pull up resistor required as the device has an internal pull up resistor. 4. t plh - propagation delay is measured from the 3.75 ma level on the high to low transition of the input current pulse to the 1.5 v level on the low to high transition of the output voltage pulse. 5. t phl - propagation delay is measured from the 3.75 ma level on the low to high transition of the input current pulse to the 1.5 v level on the high to low transition of the output voltage pulse. 6. t r - rise time is measured from the 90% to the 10% levels on the low to high transition of the output pulse. 7. t f - fall time is measured from the 10% to the 90% levels on the high to low transition of the output pulse. 8. t elh - enable input propagation delay is measured from the 1.5 v level on the high to low transition of the input voltage pulse to the 1.5 v level on the low to high transition of the output voltage pulse. 9. t ehl - enable input propagation delay is measured from the 1.5 v level on the low to high transition of the input voltage pulse to the 1.5 v level on the high to low transition of the output voltage pulse. 10. cm h - the maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., v out > 2.0 v). measured in volts per microsecond (v/?). 11. cm l - the maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low output state (i.e., v out < 0.8 v). measured in volts per microsecond (v/?). 12. device considered a two-terminal device: pins 1,2,3 and 4 shorted together, and pins 5,6,7 and 8 shorted together. notes dc characteristics test conditions symbol min typ** max unit high level output current (v cc = 5.5 v, v o = 5.5 v) i oh 100 a (i f = 250 ?, v e = 2.0 v) (note 2) low level output current (v cc = 5.5 v, i f = 5 ma) v ol .35 0.6 v (v e = 2.0 v, i cl = 13 ma) (note 2) input threshold current (v cc = 5.5 v, v o = 0.6 v, i ft 35ma v e = 2.0 v, i ol = 13 ma) transfer characteristics (t a = -40 c to +85 c unless otherwise specified.) high speed-10 mbit/s logic gate optocouplers www.fairchildsemi.com 4 of 11 7/9/01 ds300202 single-channel dual-channel 6n137 hcpl-2630 hcpl-2601 hcpl-2631 hcpl-2611
high speed-10 mbit/s logic gate optocouplers ds300202 7/9/01 5 of 11 www.fairchildsemi.com fig.1 low level output voltage vs. ambient temperature t a - ambient temperature ( ?c) t a - ambient temperature ( ?c) t a - ambient temperature ( ?c) -40 -20 0 20 40 60 80 v ol -low level output voltage (v) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i ol = 16 ma i f - forward current (ma) fig. 4 low level output current vs. ambient temperature -40 -20 0 20 40 60 80 i ol - low level output current (ma) 20 25 30 35 40 45 50 i f = 5 ma i f = 10 ma i f = 15 ma fig. 5 input threshold current vs. ambient temperature -40 -20 0 20 40 60 80 i ft - input threshold current (ma) 1 2 3 4 r l = 350 1 r l = 1k 1 r l = 4k 1 fig. 6 output voltage vs. input forward current 0123456 v o - output voltage (v) 0 1 2 3 4 5 6 r l = 350 1 r l = 1k 1 r l =4k 1 i ol = 6.4 ma i ol = 9.6 ma i ol = 12.8 ma conditions: i f = 5 ma v e = 2 v v cc = 5.5v conditions: v cc = 5.0 v v o = 0.6 v fig. 2 input diode forward voltage vs. forward current v f - forward voltage (v) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 i f = forward current (ma) 0.001 0.01 0.1 1 10 16 30 conditions: v cc = 5 v v e = 2 v v ol = 0.6 v fig.3 switching time vs. forward current i f - forward current (ma) 5 7 9 11 13 15 t p - propagation delay (ns) 0 20 40 60 80 100 120 v cc = 5 v r l = 1 k (t plh ) r l = 4 k 1 (t plh ) r l = 350 1 (t plh ) r l = 1 k 1 r l = 4 k 1 r l = 350 k 1 (t phl ) 1 single-channel dual-channel 6n137 hcpl-2630 hcpl-2601 hcpl-2631 hcpl-2611 typical performance curves
fig. 7 pulse width distortion vs. temperature t a - temperature ( ? c) t a - temperature ( ? c) -60 -40 -20 0 20 40 60 80 100 pwd - pulse width distortion (ns) 0 20 40 60 80 r l = 4 k 1 r l = 1 k 1 r l = 350 1 f conditions: i = 7.5 ma v cc = 5 v fig. 8 rise and fall time vs. temperature -60 -40 -20 0 20 40 60 80 100 tr/tf - rise and fall time (ns) 0 100 200 300 400 500 600 l r = 4 k 1 (tr) conditions: i f = 7.5 ma v cc = 5 v r l = 1 k 1 (tr) r l = 350 1 (tr) r l = 1 k 1 r l = 4 k 1 (tf) r l = 350 1 fig. 9 enable propagation delay vs. temperature t a -temperature ( ? c) -60 -40 -20 0 20 40 60 80 100 t e -enable propagation delay (ns) 0 20 40 60 80 100 120 rl = 4 k 1 (telh) r l = 1 k 1 (telh) r l = 350 1 (telh) r l = 350 1 r l = 1 k 1 r l = 4 k 1 (tehl) ] fig. 10 switching time vs. temperature t a -temperature ( ? c) -60 -40 -20 0 20 40 60 80 100 t p -propagation delay (ns) 20 40 60 80 100 120 rl = 1 k 1 tplh rl = 350 1 tplh rl = 4 k 1 tplh rl = 1 k 1 rl = 4 k 1 rl = 350 1 tphl fig. 11 high level output current vs. temperature t a -temperature ( ? c) -60 -40 -20 0 20 40 60 80 100 i o h -high level output current (a) 0 5 10 15 20 v cc = 5.5 v conditions: v o = 5.5 v v e = 2.0 v i f = 250 a ] ] high speed-10 mbit/s logic gate optocouplers www.fairchildsemi.com 6 of 11 7/9/01 ds300202 single-channel dual-channel 6n137 hcpl-2630 hcpl-2601 hcpl-2631 hcpl-2611
47 1 phl t f i = 7.5 ma 1.5 v 90% 10% 7.5 ma +5v 1.5 v 3.0 v 1.5 v 3 2 1 4 8 7 6 5 4 5 pulse 1 2 3 generator tr = 5ns z = 50 1 o 8 7 6 +5v gnd plh t i = 3.75 ma f output o (v ) input (i ) f output (v ) o f t r t cc v output (v ) o l r c l (i ) input f monitor o z = 50 pulse generator tr = 5ns 1 (v ) e input monitor gnd v cc o (v ) output l r l c (v ) output o input (v ) e ehl tt elh bypass .1 f e bypass .1 f e fig. 12 test circuit and waveforms for t plh , t phl, t r and t f . fig. 13 test circuit t ehl and t elh . high speed-10 mbit/s logic gate optocouplers ds300202 7/9/01 7 of 11 www.fairchildsemi.com single-channel dual-channel 6n137 hcpl-2630 hcpl-2601 hcpl-2631 hcpl-2611
+5v peak 3 2 1 4 8 7 6 5 gnd v cc o (v ) output 350 1 v cm ff v a b pulse gen i f cm v 0v o v 5v switching pos. (a), i = 0 f o v (max) cm 0.5 v o v switching pos. (b), i = 7.5 ma f h cm l v (min) o bypass .1 f e fig. 14 test circuit common mode transient immunity high speed-10 mbit/s logic gate optocouplers www.fairchildsemi.com 8 of 11 7/9/01 ds300202 single-channel dual-channel 6n137 hcpl-2630 hcpl-2601 hcpl-2631 hcpl-2611
high speed-10 mbit/s logic gate optocouplers ds300202 7/9/01 9 of 11 www.fairchildsemi.com single-channel dual-channel 6n137 hcpl-2630 hcpl-2601 hcpl-2631 hcpl-2611 package dimensions (through hole) 0.200 (5.08) 0.140 (3.55) 0.100 (2.54) typ 0.022 (0.56) 0.016 (0.41) 0.020 (0.51) min 0.390 (9.91) 0.370 (9.40) 0.270 (6.86) 0.250 (6.35) 3 0.070 (1.78) 0.045 (1.14) 2 41 56 7 8 0.300 (7.62) typ 0.154 (3.90) 0.120 (3.05) 0.016 (0.40) 0.008 (0.20) 15 max pin 1 i d. seating plane package dimensions (surface mount) lead coplanarity : 0.004 (0.10) max 0.270 (6.86) 0.250 (6.35) 0.390 (9.91) 0.370 (9.40) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) typ 0.020 (0.51) min 0.070 (1.78) 0.045 (1.14) 0.300 (7.62) typ 0.405 (10.30) min 0.315 (8.00) min 0.045 [1.14] 32 1 4 567 8 0.016 (0.41) 0.008 (0.20) pin 1 id. package dimensions (0.4"lead spacing) 0.200 (5.08) 0.140 (3.55) 0.100 (2.54) typ 0.022 (0.56) 0.016 (0.41) 0.004 (0.10) min 0.390 (9.91) 0.370 (9.40) 0.270 (6.86) 0.250 (6.35) 3 0.070 (1.78) 0.045 (1.14) 2 41 56 7 8 0.400 (10.16) typ 0.154 (3.90) 0.120 (3.05) 0.016 (0.40) 0.008 (0.20) 0 to 15 pin 1 id. seating plane recommended pad layout for surface mount leadform 0.070 (1.78) 0.060 (1.52) 0.030 (0.76) 0.100 (2.54) 0.295 (7.49) 0.415 (10.54) note all dimensions are in inches (millimeters)
high speed-10 mbit/s logic gate optocouplers 4.0 0.1 1.55 0.05 user direction of feed 4.0 0.1 1.75 0.10 7.5 0.1 16.0 0.3 12.0 0.1 0.30 0.05 13.2 0.2 4.90 0.20 0.1 max 10.30 0.20 10.30 0.20 1.6 0.1 qt carrier tape specifications (?d? taping orientation) ordering information s .s surface mount lead bend sd .sd surface mount; tape and reel w .w 0.4 lead spacing order entry option identifier description www.fairchildsemi.com 10 of 11 7/9/01 ds300202 single-channel dual-channel 6n137 hcpl-2630 hcpl-2601 hcpl-2631 hcpl-2611
marking information re?w pro?e 1 2 6 4 3 5 de?itions 1 fairchild logo 2 device number 3 vde mark (note: only appears on parts ordered with vde option ?see order entry table) 4 two digit year code, e.g., ?3 5 two digit work week ranging from ?1 to ?3 6 assembly package code 2601 t1 yy xx v peak reflow temperature: 225 c (package surface temperature) time of temperature higher than 183 c for 60 150 seconds one time soldering reflow is recommended 215 c, 10 30 s 225 c peak time (minute) 0 300 250 200 150 100 50 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 temperature ( c) time above 183 c, 60 150 sec ramp up = 3 c/sec
disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production isoplanar? littlefet? microcoupler? microfet? micropak? microwire? msx? msxpro? ocx? ocxpro? optologic ? optoplanar? pacman? pop? fast ? fastr? fps? frfet? globaloptoisolator? gto? hisec? i 2 c? i-lo ? implieddisconnect? rev. i13 acex? activearray? bottomless? coolfet? crossvolt ? dome? ecospark? e 2 cmos? ensigna? fact? fact quiet series? power247? poweredge? powersaver? powertrench ? qfet ? qs? qt optoelectronics? quiet series? rapidconfigure? rapidconnect? serdes? silent switcher ? smart start? spm? stealth? superfet? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic ? tinyopto? trutranslation? uhc? ultrafet ? vcx? across the board. around the world.? the power franchise ? programmable active droop?

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